In a processor for a computer, on-board registers having data or instructions are accessed frequently, especially by the arithmetic logic unit (ALU). For this purpose, a register (or row) selection system is utilized to select a register in a register set for writing or reading data to or from the register. FIG. 1 shows a conventional register selection system 11, which includes a buffer 13 and a decode array 14, for addressing a set of registers 16. The buffer 13 receives an address a (herein, boldface letters designate a vector of bits) having a width n (i.e., n bits) and converts the address into a dual rail representation having two complementary components AH, AL, both having a width n. The decode array 14, typically produced from not-or logic (NOR) gates, receives the components AH, AL, decodes the. components AH, AL, and produces 2.sup.n register selects 15 for registers 16. One of the register selects 15 is asserted, while the remainder of the register selects 15 is deasserted, so that only one register is selected from the set of registers 16 based upon the address a.
Oftentimes, it is necessary to select a register 16 based upon the sum of two addresses. This concept can be expressed mathematically as follows: a+b=K, where a is an offset, b is a base, and K is a constant that defines the desired register location. A conventional register selection system 17 that implements this functionality is set forth in FIG. 2. Referring to FIG. 2, an offset address a and a base address b, both having a width n, are communicated to an adder 19, which is clocked by a clock CK. The adder 19 mathematically sums the offset address a and the base address b in order to produce a result S. The result S is output in a dual rail manner via complementary components SH, SL, both having a width of (n+1). A decode array 21 receives the components SH, SL, decodes the components SH, SL, and produces 2.sup.n+1 register selects 15'. One of the register selects 15' is asserted, while the remainder of the register selects 15' is deasserted, so that only one of the registers 16 is selected. Moreover, the register selection system 17 of FIG. 2 produces more register selects than the register selection system 11 of FIG. 1, because of the summing operation that occurs in the adder 19.
Producing a register select 15' based upon a constant K that is the sum of two numbers is a common requirement in processor designs. Unfortunately, the register selection system 17 of FIG. 2 involves the inclusion of the adder 19, which makes the computation time depend on the delay produced by the carry propagation associated with the addition operation. As a result of the carry propagation, the response time of the system 17 is drastically reduced. In high performance processors, the system 17 of FIG. 2 is not a desirable option because of the serious performance, penalty resulting from the carry propagation.
In J. Cortadella and J. N. Llaberia, "Evaluation Of A+B=K Conditions Without Carry Propagation," IEEE Transactions On Computers, vol. 41, no. 11, pp. 1484-1488 (1992), it was recognized that the response time of parallel adders is mainly limited by the carry propagation delay. In the context of parallel adders, the authors proposed a theorem and circuit design, shown herein in FIG. 3, for evaluating when the addition of two numbers is equal to another number K without having to perform a summing operation with its attendant carry propagation. Elimination of the carry propagation reduces the response time associated with the parallel adders.
As illustrated in FIG. 3, the Cortadella/Llaberia circuit 23 includes a plurality of logically parallel cells 25. Each of the cells 25 receives a generate bit g.sub.i from a previous stage, a propagate bit p.sub.i from a previous stage, a bit k.sub.i of the result K, and a bit v.sub.i-1 from the neighboring cell corresponding with a bit of lessor value. Each cell 25 produces a bit v.sub.i for its neighboring cell 25 corresponding with a bit of higher value. Based upon the aforementioned inputs, g.sub.i, p.sub.i, k.sub.i, and v.sub.i-1, each cell 25 produces a bit z.sub.i for not-or (NOR) logic 26. The NOR logic 26 generates an output Z based upon the plurality of inputs Z.sub.i. Based upon its logic state, the output Z indicates whether or not the two numbers equal K.
Although the Cortadella/Llaberia theorem and circuit 23 of FIG. 3 have merit for parallel adder configurations, it has not been applied to or proposed in connection with a register selection system 17, as shown in FIG. 2. In fact, use of the Cortadella/Llaberia theorem and circuit 23 of FIG. 3 to eliminate the adder 19 of FIG. 2 would require an undesirable number of circuit cells 25 as well as processor space and complexity, as each cell 25 would need to be replicated once for each register.
Hence, a heretofore unaddressed need exists in the industry for systems and methods for enhancing the speed at which the selection of a register can be accomplished when the selection is based upon a constant that is the sum of two address values.